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PRELIMINARY
SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY
28F400B3, 28F800B3, 28F160B3, 28F320B3 28F008B3, 28F016B3, 28F032B3
Flexible SmartVoltage Technology 2.7 V-3.6 V Read/Program/Erase 12 V VPP Fast Production Programming 2.7 V or 1.65 V I/O Option Reduces Overall System Power High Performance 2.7 V-3.6 V: 90 ns Max Access Time 3.0 V-3.6 V: 80 ns Max Access Time Optimized Block Sizes Eight 8-KB Blocks for Data, Top or Bottom Locations Up to Sixty-Three 64-KB Blocks for Code Block Locking VCC-Level Control through WP# Low Power Consumption 10 mA Typical Read Current Absolute Hardware-Protection VPP = GND Option VCC Lockout Voltage Extended Temperature Operation -40 C to +85 C
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Flash Data Integrator Software Flash Memory Manager System Interrupt Manager Supports Parameter Storage, Streaming Data (e.g., Voice) Automated Program and Block Erase Status Registers Extended Cycling Capability Minimum 100,000 Block Erase Cycles Guaranteed Automatic Power Savings Feature Typical ICCS after Bus Inactivity Standard Surface Mount Packaging 48-Ball BGA* Package 48-Lead TSOP Package 40-Lead TSOP Package Footprint Upgradeable Upgrade Path for 4-, 8-, 16-, and 32Mbit Densities ETOXTM VI (0.25 ) Flash Technology
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The Smart 3 Advanced Boot Block, manufactured on Intel's latest 0.25 technology, represents a featurerich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability (2.7 V read, program and erase) with high-speed, low-power operation. Several new features have been added, including the ability to drive the I/O at 1.65 V, which significantly reduces system active power and interfaces to 1.65 V controllers. A new blocking scheme enables code and data storage within a single device. Add to this the Intel-developed Flash Data Integrator (FDI) software, and you have a cost-effective, monolithic code plus data storage solution. Smart 3 Advanced Boot Block products will be available in 40lead and 48-lead TSOP and 48-ball BGA* packages. Additional information on this product family can be obtained by accessing Intel's WWW page: http://www.intel.com/design/flash.
July 1998
Order Number: 290580-005
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F400B3, 28F800/008B3, 28F160/016B3, 38F320/032B3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel's Website at http://www.intel.com
COPYRIGHT (c) INTEL CORPORATION 1996, 1997,1998 *Third-party brands and names are the property of their respective owners CG-041493
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PAGE 1.0 INTRODUCTION .............................................5 1.1 Smart 3 Advanced Boot Block Flash Memory Enhancements ..............................5 1.2 Product Overview.........................................6 2.0 PRODUCT DESCRIPTION..............................6 2.1 Package Pinouts ..........................................6 2.2 Block Organization .....................................11 2.2.1 Parameter Blocks ................................11 2.2.2 Main Blocks .........................................11 3.0 PRINCIPLES OF OPERATION .....................11 3.1 Bus Operation ............................................12 3.1.1 Read....................................................13 3.1.2 Output Disable.....................................13 3.1.3 Standby ...............................................13 3.1.4 Deep Power-Down / Reset ..................13 3.1.5 Write....................................................13 3.2 Modes of Operation....................................14 3.2.1 Read Array ..........................................14 3.2.2 Read Identifier .....................................15 3.2.3 Read Status Register ..........................16 3.2.4 Program Mode.....................................16 3.2.5 Erase Mode .........................................17 3.3 Block Locking.............................................20 3.3.1 WP# = VIL for Block Locking................20 3.3.2 WP# = VIH for Block Unlocking ............20 3.4 VPP Program and Erase Voltages ..............20 3.4.1 VPP = VIL for Complete Protection .......20
SMART 3 ADVANCED BOOT BLOCK
CONTENTS
PAGE 3.5 Power Consumption ...................................20 3.5.1 Active Power .......................................21 3.5.2 Automatic Power Savings (APS) .........21 3.5.3 Standby Power ....................................21 3.5.4 Deep Power-Down Mode.....................21 3.6 Power-Up/Down Operation.........................21 3.6.1 RP# Connected to System Reset ........21 3.6.2 VCC, VPP and RP# Transitions .............21 3.7 Power Supply Decoupling ..........................22 4.0 ELECTRICAL SPECIFICATIONS..................23 4.1 Absolute Maximum Ratings ........................23 4.2 Operating Conditions..................................24 4.3 Capacitance ...............................................24 4.4 DC Characteristics .....................................25 4.5 AC Characteristics--Read Operations .......28 4.6 AC Characteristics--Write Operations........30 4.7 Program and Erase Timings .......................31 5.0 RESET OPERATIONS ..................................33 6.0 ORDERING INFORMATION..........................34 7.0 ADDITIONAL INFORMATION .......................36 APPENDIX A: Write State Machine Current/Next States.....................................37 APPENDIX B: Access Time vs. Capacitive Load...........................................38 APPENDIX C: Architecture Block Diagram ......39 APPENDIX D: Word-Wide Memory Map Diagrams......................................................40 APPENDIX E: Byte Wide Memory Map Diagrams......................................................43 APPENDIX F: Program and Erase Flowcharts .45
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Description
REVISION HISTORY
Number -001 -002 Original version Section 3.4, VPP Program and Erase Voltages, added Updated Figure 9: Automated Block Erase Flowchart Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table) Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes) IPPR maximum specification change from 25 A to 50 A Program and Erase Suspend Latency specification change Updated Appendix A: Ordering Information (included 8 M and 4 M information) Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes) Minor wording changes Combined byte-wide specification (previously 290605) with this document Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V) Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4) Improved several DC characteristics (Section 4.4) Improved several AC characteristics (Sections 4.5 and 4.6) Combined 2.7 V and 1.8 V DC characteristics (Section 4.4) Added 5 V VPP read specification (Section 3.4) Removed 120 ns and 150 ns speed offerings Moved Ordering Information from Appendix to Section 6.0; updated information Moved Additional Information from Appendix to Section 7.0 Updated figure Appendix B, Access Time vs. Capacitive Load Updated figure Appendix C, Architecture Block Diagram Moved Program and Erase Flowcharts to Appendix E Updated Program Flowchart Updated Program Suspend/Resume Flowchart Minor text edits throughout. Added 32-Mbit density Added 98H as a reserved command (Table 4) A1-A20 = 0 when in read identifier mode (Section 3.2.2) Status register clarification for SR3 (Table 7) VCC and VCCQ absolute maximum specification = 3.7 V (Section 4.1) Combined IPPW and ICCW into one specification (Section 4.4) Combined IPPE and ICCE into one specification (Section 4.4) Max Parameter Block Erase Time (t WHQV2/tEHQV2) reduced to 4 sec (Section 4.7) Max Main Block Erase Time (t WHQV3/tEHQV3) reduced to 5 sec (Section 4.7) Erase suspend time @ 12 V (t WHRH2/tEHRH2) changed to 5 s typical and 20 s maximum (Section 4.7) Ordering Information updated (Section 6.0) Write State Machine Current/Next States Table updated (Appendix A) Program Suspend/Resume Flowchart updated (Appendix F) Erase Suspend/Resume Flowchart updated (Appendix F) Text clarifications throughout BGA package diagrams corrected (Figures 3 and 4) IPPD test conditions corrected (Section 4.4) 32-Mbit ordering information corrected (Section 6) BGA package top side mark information added (Section 6)
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-004
-005
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1.0
SMART 3 ADVANCED BOOT BLOCK
INTRODUCTION
1.1
Smart 3 Advanced Boot Block Flash Memory Enhancements
This datasheet contains the specifications for the Advanced Boot Block flash memory family, which is optimized for low power, portable systems. This family of products features 1.65 V-2.5 V or 2.7 V- 3.6 V I/Os and a low VCC/VPP operating range of 2.7 V-3.6 V for read, program, and erase operations. In addition this family is capable of fast programming at 12 V. Throughout this document, the term "2.7 V" refers to the full voltage range 2.7 V-3.6 V (except where noted otherwise) and "VPP = 12 V" refers to 12 V 5%. Section 1.0 and 2.0 provide an overview of the flash memory family including applications, pinouts and pin descriptions. Section 3.0 describes the memory organization and operation for these products. Sections 4.0 and 5.0 contain the operating specifications. Finally, Sections 6.0 and 7.0 provide ordering and other reference information.
The Smart 3 Advanced Boot Block flash memory features * * * Enhanced blocking for easy segmentation of code and data or additional design flexibility Program Suspend to Read command VCCQ input of 1.65 V-2.5 V on all I/Os. See Figures 1 through 4 for pinout diagrams and VCCQ location Maximum program and erase time specification for improved data storage.
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Table 1. Smart 3 Advanced Boot Block Feature Summary Feature VCC Read Voltage VCCQ I/O Voltage VPP Program/Erase Voltage Bus Width Speed Memory Arrangement 28F008B3, 28F016B3, 28F032B3(1) 28F400B3(2), 28F800B3, 28F160B3, 28F320B3 Reference Section 4.2, 4.4 Section 4.2, 4.4 Section 4.2, 4.4 Table 3 Section 4.5 Section 2.2
2.7 V- 3.6 V 1.65 V-2.5 V or 2.7 V- 3.6 V 2.7 V- 3.6 V or 11.4 V- 12.6 V 8-bit 16 bit
80 ns, 90 ns, 100 ns, 110 ns 1024 Kbit x 8 (8 Mbit), 2048 Kbit x 8 (16 Mbit), 4096 Kbit x 8 (32 Mbit) 256 Kbit x 16 (4 Mbit), 512 Kbit x 16 (8 Mbit), 1024 Kbit x 16 (16 Mbit) 2048 Kbit x 16 (32 Mbit)
Blocking (top or bottom)
Eight 8-Kbyte parameter blocks and Seven 64-Kbyte blocks (4-Mbit) or Fifteen 64-Kbyte blocks (8-Mbit) or Thirty-one 64-Kbyte main blocks (16-Mbit) Sixty-three 64-Kbyte main blocks (32-Mbit) WP# locks/unlocks parameter blocks All other blocks protected using V PP Extended: -40 C to +85 C 100,000 cycles 40-lead 48-Ball BGA* CSP(2) TSOP(1), 48-Lead TSOP, 48-Ball BGA CSP(2)
Section 2.2 Appendix D
Locking Operating Temperature Program/Erase Cycling Packages
Section 3.3 Table 8 Section 4.2, 4.4 Section 4.2, 4.4 Figure 3, Figure 4
NOTES: 1. 4-Mbit and 32-Mbit density not available in 40-lead TSOP. 2. 4-Mbit density not available in BGA* CSP.
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1.2
Product Overview
Intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins: VCC for read operation, VCCQ for output swing, and VPP for program and erase operation. All Smart 3 Advanced Boot Block flash memory products provide program/erase capability at 2.7 V or 12 V [for fast production programming] and read with VCC at 2.7 V. Since many designs read from the flash memory a large percentage of the time, 2.7 V VCC operation can provide substantial power savings. The Smart 3 Advanced Boot Block flash memory products are available in either x8 or x16 packages in the following densities: (see Ordering Information for availability.) * 4-Mbit (4,194,304-bit) flash memory organized as 256 Kwords of 16 bits each or 512 Kbytes of 8-bits each 8-Mbit (8,388,608-bit) flash memory organized as 512 Kwords of 16 bits each or 1024 Kbytes of 8-bits each 16-Mbit (16,777,216-bit) flash memory organized as 1024 Kwords of 16 bits each or 2048 Kbytes of 8-bits each 32-Mbit (33,554,432-bit) flash memory organized as 2048 Kwords of 16 bits each or 4096 Kbytes of 8-bits each
The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. The status register indicates the status of the WSM by signifying block erase or word program completion and status. The Smart 3 Advanced Boot Block flash memory is also designed with an Automatic Power Savings (APS) feature which minimizes system current drain, allowing for very low power designs. This mode is entered following the completion of a read cycle (approximately 300 ns later). The RP# pin provides additional protection against unwanted command writes that may occur during system reset and power-up/down sequences due to invalid system bus conditions (see Section 3.6). Section 3.0 gives detailed explanation of the different modes of operation. Complete current and voltage specifications can be found in the DC Characteristics section. Refer to AC Characteristics for read, program and erase performance specifications.
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2.0
PRODUCT DESCRIPTION
The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. The upper two (or lower two) parameter blocks can be locked to provide complete code security for system initialization code. Locking and unlocking is controlled by WP# (see Section 3.3 for details).
This section explains device pin description and package pinouts.
2.1
Package Pinouts
The Smart 3 Advanced Boot Block flash memory is available in 40-lead TSOP (x8, Figure 1), 48-lead TSOP (x16, Figure 2) and 48-ball BGA packages (x8 and x16, Figure 3 and Figure 4 respectively). In all figures, pin changes necessary for density upgrades have been circled.
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A16 A15 A14 A13 A12 A11 A9 A8 WE# RP# VPP WP# A18 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Advanced Boot Block 40-Lead TSOP 10 mm x 20 mm TOP VIEW
SMART 3 ADVANCED BOOT BLOCK
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A17 GND A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VCCQ VCC NC DQ3 DQ2 DQ1 DQ0 OE# GND CE# A0
16 M 8M
0580_01
NOTES: 1. 40-Lead TSOP available for 8- and 16-Mbit densities only. 2. Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pin 38.
Figure 1. 40-Lead TSOP Package for x8 Configurations
32 M
16 M 8M 4M
A15 A14 A13 A12 A11 A10 A9 A8 NC A20 WE# RP# VPP WP# A19 A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Advanced Boot Block 48-Lead TSOP 12 mm x 20 mm TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 VCCQ GND DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0
0580_02
NOTE: Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pins 9 and 15.
Figure 2. 48-Lead TSOP Package for x16 Configurations
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4 5 16M 6 7 8 VPP WP# 8M A20 A7 A4 RP# 32M A19 A18 A5 A2 A21 A6 A3 A1 NC D2 NC CE# A0 NC D3 NC D0 GND
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2
3
A
A14
A12
A8
B
A15
A10
WE#
C
A16
A13
A9
D
A17
NC
D5
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VCCQ
A11
D6
F
GND
D7
NC
D4
VCC
NC
D1
OE#
0580_04
NOTE: 1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address solder balls. Routing is not recommended in this area. A20 is the upgrade address for the 16-Mbit device. A21 is the upgrade address for the 32-Mbit device. 2. 4-Mbit density not available in BGA* CSP.
Figure 3. x8 48-Ball BGA* Chip Size Package (Top View, Ball Down)
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1 2 3 4 5 A A13 A11 A8 VPP WP# 8M B A14 A10 WE# RP# 32M C A15 A12 A9 A20 A18 D A16 D14 D5 D11 D2 E VCCQ D15 D6 D12 D3
SMART 3 ADVANCED BOOT BLOCK
6 16M A19
7
8
A7
A4
A17
A5
A2
A6
A3
A1
D8
CE#
A0
D9
D0
GND
F
GND
D7
D13
D4
VCC
D10
D1
OE#
0580_03
NOTES: 1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address solder balls. Routing is not recommended in this area. A19 is the upgrade address for the 16-Mbit device. A20 is the upgrade address for the 32-Mbit device. 2. 4-Mbit density not available in BGA* CSP.
Figure 4. x16 48-Ball BGA* Chip Size Package (Top View, Ball Down)
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Name and Function
The pin descriptions table details the usage of each device pin. Table 2. Smart 3 Advanced Boot Block Pin Descriptions Symbol A0-A21 Type INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or erase cycle. 28F008B3: A[0-19], 28F016B3: A[0-20], 28F032B3: A[0-21], 28F800B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19], 28F320B3: A[0-20] DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched. Outputs array, identifier and status register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled. DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Data is internally latched. Outputs array and identifier data. The data pins float to tri-state when the chip is de-selected. Not included on x8 products. CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. OUTPUT ENABLE: Enables the device's outputs through the data buffers during a read operation. OE# is active low. WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse. RESET/DEEP POWER-DOWN: Uses two voltage levels (V IL, VIH) to control reset/deep power-down mode. When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to High-Z, resets the Write State Machine, and minimizes current levels (I CCD). When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode.
DQ0-DQ7
INPUT/OUTPUT
DQ8-DQ15
INPUT/OUTPUT
CE#
INPUT
OE# WE#
INPUT INPUT
RP#
INPUT
WP#
INPUT
WRITE PROTECT: Provides a method for locking and unlocking the two lockable parameter blocks. When WP# is at logic low, the lockable blocks are locked, preventing program and erase operations to those blocks. If a program or erase operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5 [erase] will be set to indicate the operation failed. When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased. See Section 3.3 for details on write protection.
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Symbol VCCQ VCC VPP
SMART 3 ADVANCED BOOT BLOCK
Table 2. Smart 3 Advanced Boot Block Pin Descriptions (Continued) Type INPUT Name and Function OUTPUT VCC: Enables all outputs to be driven to 1.8 V - 2.5 V while the VCC is at 2.7 V-3.3 V. If the V CC is regulated to 2.7 V-2.85 V, VCCQ can be driven at 1.65 V-2.5 V to achieve lowest power operation (see Section 4.4, DC Characteristics. This input may be tied directly to V CC (2.7 V-3.6 V). DEVICE POWER SUPPLY: 2.7 V-3.6 V PROGRAM/ERASE POWER SUPPLY: Supplies power for program and erase operations. VPP may be the same as V CC (2.7 V-3.6 V) for single supply voltage operation. For fast programming at manufacturing, 11.4 V-12.6 V may be supplied to V PP. This pin cannot be left floating. Applying 11.4 V-12.6 V to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum (see Section 3.4 for details). VPP < VPPLK protects memory contents against inadvertent or unintended program and erase commands.
GND NC
GROUND: For all internal circuitry. All ground inputs must be connected. NO CONNECT: Pin may be driven or left floating.
2.2
Block Organization
2.2.2
MAIN BLOCKS
The Smart 3 Advanced Boot Block is an asymmetrically-blocked architecture that enables system integration of code and data within a single flash device. Each block can be erased independently of the others up to 100,000 times. For the address locations of each block, see the memory maps in Appendix D. 2.2.1 PARAMETER BLOCKS
After the parameter blocks, the remainder of the array is divided into equal size main blocks (65,536 bytes / 32,768 words) for data or code storage. The 4-Mbit device contains seven main blocks; 8-Mbit device contains fifteen main blocks; 16-Mbit flash has thirty-one main blocks; 32-Mbit has sixty-three main blocks.
3.0
PRINCIPLES OF OPERATION
The Smart 3 Advanced Boot Block flash memory architecture includes parameter blocks to facilitate storage of frequently updated small parameters (e.g., data that would normally be stored in an EEPROM). By using software techniques, the wordrewrite functionality of EEPROMs can be emulated. Each device contains eight parameter blocks of 8-Kbytes/4-Kwords (8192 bytes/4,096 words) each.
Flash memory combines EEPROM functionality with in-circuit electrical program and erase capability. The Smart 3 Advanced Boot Block flash memory family utilizes a Command User Interface (CUI) and automated algorithms to simplify program and erase operations. The CUI allows for 100% CMOS-level control inputs and fixed power supplies during erasure and programming.
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When VPP < VPPLK, the device will only execute the following commands successfully: Read Array, Read Status Register, Clear Status Register and Read Identifier. The device provides standard EEPROM read, standby and output disable operations. Manufacturer identification and device identification data can be accessed through the CUI. All functions associated with altering memory contents, namely program and erase, are accessible via the CUI. The internal Write State Machine (WSM) completely automates program and erase operations while the CUI signals the start of an operation and the status register reports status. The CUI handles the WE# interface to the data and address latches, as well as system status requests during WSM operation.
3.1
Bus Operation
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DQ0-7 DOUT High Z High Z High Z DIN DQ8-15 DOUT High Z High Z High Z DIN
Smart 3 Advanced Boot Block flash memory devices read, program and erase in-system via the local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash component: CE#, OE#, WE# and RP#. These bus operations are summarized in Table 3.
Table 3. Bus Operations(1) Mode Read (Array, Status, or Identifier) Output Disable Standby Reset Write Note 2-4 2 2 2, 7 2, 5-7 RP# VIH VIH VIH VIL VIH CE# VIL VIL VIH X VIL OE# VIL VIH X X VIH WE# VIH VIH X X VIL
NOTES: 1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15] 2. X must be VIL, VIH for control pins and addresses. 3. See DC Characteristics for VPPLK, VPP1, VPP2, VPP3, VPP4 voltages. 4. Manufacturer and device codes may also be accessed in read identifier mode (A -A21 = 0). See Table 4. 1 5. Refer to Table 6 for valid DIN during a write operation. 6. To program or erase the lockable blocks, hold WP# at VIH. 7. RP# must be at GND 0.2 V to meet the maximum deep power-down current specified.
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3.1.1 READ The flash memory has four read modes available: read array, read identifier, read status and read query. These modes are accessible independent of the VPP voltage. The appropriate Read Mode command must be issued to the CUI to enter the corresponding mode. Upon initial device power-up or after exit from reset, the device automatically defaults to read array mode. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control; when active it enables the flash memory device. OE# is the data output control and it drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at VIH. Figure 7 illustrates a read cycle. 3.1.2 OUTPUT DISABLE
SMART 3 ADVANCED BOOT BLOCK
If RP# is taken low for time tPLPH during a program or erase operation, the operation will be aborted and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. The abort process goes through the following sequence: When RP# goes low, the device shuts down the operation in progress, a process which takes time tPLRH to complete. After this time tPLRH, the part will either reset to read array mode (if RP# has gone high during tPLRH, Figure 9B) or enter reset mode (if RP# is still logic low after tPLRH, Figure 9C). In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL/tPHEL must be waited before a read or write operation is initiated, as discussed in the previous paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than when RP# goes high. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, processor expects to read from the flash memory. Automated flash memories provide status information when read during program or block erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel's Flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 3.1.5 WRITE
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins are placed in a high-impedance state. 3.1.3 STANDBY
Deselecting the device by bringing CE# to a logichigh level (VIH) places the device in standby mode, which substantially reduces device power consumption without any latency for subsequent read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete. 3.1.4 DEEP POWER-DOWN / RESET
From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required until the initial read access outputs are valid. A delay (tPHWL or tPHEL) is required after return from reset before a write can be initiated. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, and the status register is set to 80H. This case is shown in Figure 9A.
A write takes place when both CE# and WE# are low and OE# is high. Commands are written to the Command User Interface (CUI) using standard microprocessor write timings to control flash operations. The CUI does not occupy an addressable memory location. The address and data buses are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first. Figure 8 illustrates a program and erase operation. The available commands are shown in Table 6, and Appendix A provides detailed information on moving between the different modes of operation using CUI commands.
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There are two commands that modify array data: Program (40H) and Erase (20H). Writing either of these commands to the internal Command User Interface (CUI) initiates a sequence of internallytimed functions that culminate in the completion of the requested task (unless that operation is aborted by either RP# being driven to VIL for tPLRH or an appropriate suspend command). 3.2.1 READ ARRAY
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When RP# transitions from VIL (reset) to VIH, the device defaults to read array mode and will respond to the read control inputs (CE#, address inputs, and OE#) without any additional CUI commands. When the device is in read array mode, four control signals control data output: * * * * WE# must be logic high (VIH) CE# must be logic low (VIL) OE# must be logic low (VIL) RP# must be logic high (VIH)
3.2
Modes of Operation
The flash memory has four read modes and two write modes. The read modes are read array, read identifier, read status and read query (see Appendix C). The write modes are program and block erase. Three additional modes (erase suspend to program, erase suspend to read and program suspend to read) are available only during suspended operations. These modes are reached using the commands summarized in Table 4. A comprehensive chart showing the state transitions is in Appendix A.
In addition, the address of the desired location must be applied to the address pins. If the device is not in read array mode, as would be the case after a program or erase operation, the Read Array command (FFH) must be written to the CUI before array reads can take place.
Table 4. Command Codes and Descriptions Code 00, 01, 60, 2F, C0, 98 FF 40 Device Mode Invalid/ Reserved Description Unassigned commands that should not be used. Intel reserves the right to redefine these codes for future functions.
Read Array Program Set-Up
Places the device in read array mode, such that array data will be output on the data pins. This is a two-cycle command. The first cycle prepares the CUI for a program operation. The second cycle latches addresses and data information and initiates the WSM to execute the Program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Section 3.2.4.
10 20
Alternate (See 40H/Program Set-Up) Program Set-Up Erase Set-Up Prepares the CUI for the Erase Confirm command. If the next command is not an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a "1," (b) place the device into the read status register mode, and (c) wait for another command. See Section 3.2.5.
14
PRELIMINARY
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Code D0 Device Mode Erase Confirm B0
SMART 3 ADVANCED BOOT BLOCK
Table 4. Command Codes and Descriptions (Continued) Description If the previous command was an Erase Set-Up command, then the CUI will close the address and data latches, and begin erasing the block indicated on the address pins. During erase, the device will only respond to the Read Status Register and Erase Suspend commands. The device will output status register data when CE# or OE# is toggled.
Program / Erase If a program or erase operation was previously suspended, this command will Resume resume that operation Program / Erase Issuing this command will begin to suspend the currently executing Suspend program/erase operation. The status register will indicate when the operation has been successfully suspended by setting either the program suspend (SR.2) or erase suspend (SR.6) and the WSM status bit (SR.7) to a "1" (ready). The WSM will continue to idle in the SUSPEND state, regardless of the state of all input control pins except RP#, which will immediately shut down the WSM and the remainder of the chip if it is driven to V IL. See Sections 3.2.4.1 and 3.2.5.1. Read Status Register This command places the device into read status register mode. Reading the device will output the contents of the status register, regardless of the address presented to the device. The device automatically enters this mode after a program or erase operation has been initiated. See Section 3.2.3. The WSM can set the block lock status (SR.1) , V PP status (SR.3), program status (SR.4), and erase status (SR.5) bits in the status register to "1," but it cannot clear them to "0." Issuing this command clears those bits to "0." Puts the device into the intelligent identifier read mode, so that reading the device will output the manufacturer and device codes (A 0 = 0 for manufacturer, A0 = 1 for device, all other address inputs must be 0). See Section 3.2.2.
70
50
Clear Status Register Read Identifier
90
NOTE: See Appendix A for mode transition information.
3.2.2
READ IDENTIFIER
Table 5. Read Identifier Table Device Identifier Size 28F400B3 28F008B3 28F800B3 28F016B3 28F160B3 28F032B3 28F320B3 0089H 0089H Mfr. ID 0089H 0089H -T -B (Top Boot) (Bot. Boot) 8894H D2 8892H D0 8890H D6 8896 8895H D3 8893H D1 8891H D7 8897
To read the manufacturer and device codes, the device must be in read identifier mode, which can be reached by writing the Read Identifier command (90H). Once in read identifier mode, A0 = 0 outputs the manufacturer's identification code and A0 = 1 outputs the device identifier (see Table 5) Note: A1--A21 = 0. To return to read array mode, write the Read Array command (FFH).
PRELIMINARY
15
SMART 3 ADVANCED BOOT BLOCK
3.2.3 READ STATUS REGISTER 3.2.4 PROGRAM MODE
E
The device status register indicates when a program or erase operation is complete and the success or failure of that operation. To read the status register issue the Read Status Register (70H) command to the CUI. This causes all subsequent read operations to output data from the status register until another command is written to the CUI. To return to reading from the array, issue the Read Array (FFH) command. The status register bits are output on DQ0-DQ7. The upper byte, DQ8-DQ15, outputs 00H during a Read Status Register command. The contents of the status register are latched on the falling edge of OE# or CE#. This prevents possible bus errors which might occur if status register contents change while being read. CE# or OE# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status register indicate whether or not the WSM was successful in performing the desired operation (see Table 7). 3.2.3.1 Clearing the Status Register
Programming is executed using a two-write sequence. The Program Setup command (40H) is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to program desired bits of the addressed location, then Verify the bits are sufficiently programmed. Programming the memory results in specific bits within an address location being changed to a "0." If the user attempts to program "1"s, the memory cell contents do not change and no error occurs. The status register indicates programming status: while the program sequence executes, status bit 7 is "0." The status register can be polled by toggling either CE# or OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume. When programming is complete, the Program Status bits should be checked. If the programming operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If SR.3 is set then VPP was not within acceptable limits, and the WSM did not execute the program command. If SR.1 is set, a program operation was attempted on a locked block and the operation was aborted. The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the CUI to read array mode. 3.2.4.1 Suspending and Resuming Program
The WSM sets status bits 1 through 7 to "1," and clears bits 2, 6 and 7 to "0," but cannot clear status bits 1 or 3 through 5 to "0." Because bits 1, 3, 4 and 5 indicate various error conditions, these bits can only be cleared through the Clear Status Register (50H) command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. Clear the status register before beginning another command or sequence. Note, again, that the Read Array command must be issued before data can be read from the memory array.
The Program Suspend halts the in-progress program operation to read data from another location of memory. Once the programming process starts, writing the Program Suspend command to the CUI requests that the WSM suspend the program sequence (at predetermined points in the program algorithm). The device continues to output status register data after the Program Suspend command is written. Polling status register bits SR.7 and SR.2 will determine when the program operation has been suspended (both will be set to "1"). tWHRH1/tEHRH1 specify the program suspend latency.
16
PRELIMINARY
A Read Array command can now be written to the CUI to read data from blocks other than that which is suspended. The only other valid commands while program is suspended, are Read Status Register, Read Identifier, and Program Resume. After the Program Resume command is written to the flash memory, the WSM will continue with the program process and status register bits SR.2 and SR.7 will automatically be cleared. After the Program Resume command is written, the device automatically outputs status register data when read (see Appendix F for Program Suspend and Resume Flowchart). VPP must remain at the same VPP level used for program while in program suspend mode. RP# must also remain at V IH. 3.2.5 ERASE MODE
E
SMART 3 ADVANCED BOOT BLOCK
After an erase operation, clear the status register (50H) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to place the flash in read array mode after the erase is complete. 3.2.5.1 Suspending and Resuming Erase
To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to "1." Only one block can be erased at a time. The WSM will execute a sequence of internally-timed events to program all bits within the block to "0," erase all bits within the block to "1," then verify that all bits within the block are sufficiently erased. While the erase executes, status bit 7 is a "0." When the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. If the erase operation was unsuccessful, SR.5 of the status register will be set to a "1," indicating an erase failure. If VPP was not within acceptable limits after the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a "1" to identify that VPP supply voltage was not within acceptable limits.
Since an erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase-sequence interruption in order to read data from or program data to another block in memory. Once the erase sequence is started, writing the Erase Suspend command to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase algorithm. The status register will indicate if/when the erase operation has been suspended. A Read Array/Program command can now be written to the CUI in order to read data from/ program data to blocks other than the one currently suspended. The Program command can subsequently be suspended to read yet another array location. The only valid commands while erase is suspended are Erase Resume, Program, Read Array, Read Status Register, or Read Identifier. During erase suspend mode, the chip can be placed in a pseudo-standby mode by taking CE# to VIH. This reduces active current consumption. Erase Resume continues the erase sequence when CE# = VIL. As with the end of a standard erase operation, the status register must be read and cleared before the next instruction is issued.
PRELIMINARY
17
SMART 3 ADVANCED BOOT BLOCK
E
First Bus Cycle Second Bus Cycle Oper Addr Data Oper Write Addr X X X X X X X X Data FFH 90H 70H 50H 40H / 10H 20H B0H D0H Write Write PA BA PD D0H Read Read IA X ID SRD Write Write Write Write Write Write Write
Table 6. Command Bus Definitions(1, 4)
Command Read Array Read Identifier Read Status Register Clear Status Register Program Block Erase/Confirm Program/Erase Suspend Program/Erase Resume
NOTES: 1. 2. 3. 4.
Notes
2
3
PA: Program Address PD: Program Data BA: Block Address IA: Identifier Address ID: Identifier Data SRD: Status Register Data Bus operations are defined in Table 3. Following the Intelligent Identifier command, two read operations access manufacturer and device codes. A0 = 0 for manufacturer code, A0 = 1 for device code. A1--A21 = 0. Either 40H or 10H command is valid although the standard is 40H. When writing commands to the device, the upper data bus [DQ 8-DQ15] should be either VIL or VIH, to minimize current draw.
18
PRELIMINARY
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WSMS 7 ESS 6
SMART 3 ADVANCED BOOT BLOCK
Table 7. Status Register Bit Definition ES 5 PS 4 VPPS 3 PSS 2 NOTES: BLS 1 R 0
SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed SR.5 = ERASE STATUS (ES) 1 = Error In Block Erasure 0 = Successful Block Erase SR.4 = PROGRAM STATUS (PS) 1 = Error in Word Program 0 = Successful Word Program SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK
Check Write State Machine bit first to determine word program or block erase completion, before checking program or erase status bits. When erase suspend is issued, WSM halts execution and sets both WSMS and ESS bits to "1." ESS bit remains set at "1" until an Erase Resume command is issued. When this bit is set to "1," WSM has applied the max. number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to "1," WSM has attempted but failed to program a word. The VPP status bit does not provide continuous indication of VPP level. The WSM interrogates VPP level only after the Program or Erase command sequences have been entered, and informs the system if V PP has not been switched on. The VPP is also checked before the operation is verified by the WSM. The VPP status bit is not guaranteed to report accurate feedback between VPPLK max and VPP1 min or between VPP1 max and VPP4 min. When program suspend is issued, WSM halts execution and sets both WSMS and PSS bits to "1." PSS bit remains set to "1" until a Program Resume command is issued. If a program or erase operation is attempted to one of the locked blocks, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. This bit is reserved for future use and should be masked out when polling the status register.
SR.2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed SR.1 = Block Lock Status 1 = Program/Erase attempted on locked block; Operation aborted 0 = No operation to locked blocks SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
PRELIMINARY
19
SMART 3 ADVANCED BOOT BLOCK
3.3
Block Locking
3.4
VPP Program and Erase Voltages
E
The Smart 3 Advanced Boot Block flash memory architecture features two hardware-lockable parameter blocks. 3.3.1 WP# = VIL FOR BLOCK LOCKING
Intel's Smart 3 products provide in-system programming and erase at 2.7 V. For customers requiring fast programming in their manufacturing environment, Smart 3 includes an additional lowcost 12 V programming feature. The 12 V VPP mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 V may be applied to VPP during program and erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage. During read operations or idle times, VPP may be tied to a 5 V supply. For program and erase operations, a 5 V supply is not permitted. The VPP must be supplied with either 2.7 V-3.6 V or 11.4 V- 12.6 V during program and erase operations. 3.4.1 VPP = VIL FOR COMPLETE PROTECTION
The lockable blocks are locked when WP# = VIL; any program or erase operation to a locked block will result in an error, which will be reflected in the status register. For top configuration, the top two parameter blocks (blocks #69 and #70, blocks #37 and #38 for the 16-Mbit, blocks #21 and #22 for the 8-Mbit, blocks #13 and #14 for the 4-Mbit) are lockable. For the bottom configuration, the bottom two parameter blocks (blocks #0 and #1 for 4-/8-/ 16-/32-Mbit) are lockable. Unlocked blocks can be programmed or erased normally (unless VPP is below VPPLK). 3.3.2 WP# = VIH FOR BLOCK UNLOCKING
WP# = VIH unlocks all lockable blocks. These blocks can now be programmed or erased. Note that RP# does not override WP# locking as in previous Boot Block devices. WP# controls all block locking and VPP provides protection against spurious writes. Table 8 defines the write protection methods. Table 8. Write Protection Truth Table for Advanced Boot Block Flash Memory Family VPP X VIL VPPLK VPPLK WP# X X VIL VIH RP# VIL VIH VIH VIH Write Protection Provided All Blocks Locked All Blocks Locked Lockable Blocks Locked All Blocks Unlocked
The VPP programming voltage can be held low for complete write protection of all blocks in the flash device. When VPP is below VPPLK, any program or erase operation will result in a error, prompting the corresponding status register bit (SR.3) to be set.
3.5
Power Consumption
Intel(R) Flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is selected but idle. If the CE# is deasserted, the flash enters its standby mode, where current consumption is even lower. The combination of these features can minimize memory power consumption, and therefore, overall system power consumption.
20
PRELIMINARY
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3.5.1 3.5.2
SMART 3 ADVANCED BOOT BLOCK
or the block being erased are no longer valid as the data integrity has been compromised by the abort. During deep power-down, all internal circuits are switched to a low power savings mode (RP# transitioning to VIL or turning off power to the device clears the status register).
ACTIVE POWER
With CE# at a logic-low level and RP# at a logichigh level, the device is in the active mode. Refer to the DC Characteristic tables for ICC current values. Active power is the largest contributor to overall system power consumption. Minimizing the active current could have a profound effect on system power consumption, especially for battery-operated devices. AUTOMATIC POWER SAVINGS (APS)
3.6
Power-Up/Down Operation
Automatic Power Savings provides low-power operation during read mode. After data is read from the memory array and the address lines are quiescent, APS circuitry places the device in a mode where typical current is comparable to ICCS., The flash stays in this static state with outputs valid until a new location is read. 3.5.3 STANDBY POWER
The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, VPP or VCC, powers-up first. 3.6.1 RP# CONNECTED TO SYSTEM RESET
With CE# at a logic-high level (VIH) and device in read mode, the flash memory is in standby mode, which disables much of the device's circuitry and substantially reduces power consumption. Outputs are placed in a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. System engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. This will provide a more accurate measure of application-specific power and energy requirements. 3.5.4 DEEP POWER-DOWN MODE
The use of RP# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when VCC voltages are above VLKO. Since both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the twostep command sequences. The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 3.6.2 VCC, VPP AND RP# TRANSITIONS
The deep power-down mode is activated when RP# = VIL (GND 0.2 V). During read modes, RP# going low de-selects the memory and places the outputs in a high impedance state. Recovery from deep power-down requires a minimum time of tPHQV (see AC Characteristics--Read Operations). During program or erase modes, RP# transitioning low will abort the in-progress operation. The memory contents of the address being programmed
The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after VCC transitions above VLKO (Lockout voltage), is read array mode. 21
PRELIMINARY
SMART 3 ADVANCED BOOT BLOCK
After any program or block erase operation is complete (even after VPP transitions down to VPPLK), the CUI must be reset to read array mode via the Read Array command if access to the flash memory array is desired.
3.7
Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling. System designers should consider three supply current issues: 1. Standby current levels (ICCS) 2. Read current levels (ICCR) 3. Transient peaks produced by falling and rising edges of CE#.
Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 F ceramic capacitor connected between each VCC and GND, and between its VPP and GND. These highfrequency, inherently low-inductance capacitors should be placed as close as possible to the package leads.
E
22
PRELIMINARY
E
4.0 4.1
SMART 3 ADVANCED BOOT BLOCK
NOTICE: This datasheet contains preliminary information on new products in production. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design.
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings*
Extended Operating Temperature During Read .......................... -40 C to +85 C During Block Erase and Program.......................... -40 C to +85 C Temperature Under Bias ....... -40 C to +85 C Storage Temperature................. -65 C to +125 C Voltage on Any Pin (except VCC, VCCQ and VPP) with Respect to GND ............. -0.5 V to 3.7 V (1) VPP Voltage (for Block Erase and Program) with Respect to GND ..... -0.5 V to +13.5 V(1,2,4) VCC and VCCQ Supply Voltage with Respect to GND ........... -0.2 V to +3.7 V(5) Output Short Circuit Current.....................100 mA(3)
* WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may effect device reliability.
NOTES: 1. Minimum DC voltage is -0.5 V on input/output pins, with allowable undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins is VCC + 0.5 V, with allowable overshoot to VCC + 1.5 V for periods < 20 ns. 2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. 4. VPP Program voltage is normally 2.7 V-3.6 V. 5. Minimum DC voltage is -0.5 V on VCC and VCCQ, with allowable undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on VCC and VCCQ pins is VCC + 0.5 V, with allowable overshoot to VCC + 1.5 V for periods < 20 ns.
PRELIMINARY
23
SMART 3 ADVANCED BOOT BLOCK
4.2
Operating Conditions
Parameter Operating Temperature VCC Supply Voltage 1 Notes Min -40 2.7 2.7 2.7 I/O Supply Voltage 1 2.7 1.65 1.8 Program and Erase Voltage 1 2.7 2.7 2.7 2, 3 Block Erase Cycling 3 11.4 100,000 Max +85 3.6 2.85 3.3 3.6 2.5 2.5 3.6 2.85 3.3 12.6
E
Units C Volts Volts Volts
Symbol TA VCC1 VCC2 VCC3 VCCQ1 VCCQ2 VCCQ3 VPP1 VPP2 VPP3 VPP4 Cycling
Cycles
NOTES: 1. VCC1, VCCQ1, and VPP3 must share the same supply when all three are between 2.7 V and 3.6 V. 2. During read operations or idle time, 5 V may be applied to VPP indefinitely. VPP must be at valid levels for program and erase operations 3. Applying VPP = 11.4 V-12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.4 for details.
4.3
Sym CIN COUT
Capacitance
Parameter Input Capacitance Output Capacitance Notes 1 1 Typ 6 10 Max 8 12 Units pF pF VIN = 0 V VOUT = 0 V Conditions
TA = 25 C, f = 1 MHz
NOTE: 1. Sampled, not 100% tested.
24
PRELIMINARY
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4.4
Sym ILI ILO ICCS
SMART 3 ADVANCED BOOT BLOCK
DC Characteristics(1)
VCC VCCQ Parameter Input Load Current 2.7 V-3.6 V 2.7 V-2.85 V 2.7 V-3.3 V 2.7 V-3.6 V 1.65 V-2.5 V 1.8 V-2.5 V Max 1 Typ Max 1 Typ Max Unit 1 A Test Conditions VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND VCC = VCCMax CE# = RP# = VCC or during Program/ Erase Suspend VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND RP# = GND 0.2 V VCC = VCCMax VCCQ = VCCQMax OE# = VIH , CE# =VIL f = 5 MHz, I OUT=0mA Inputs = VIL or VIH RP# = GND 0.2 V VPP VCC 2 3 50 18 10 15 200 55 30 45 45 200 2 50 18 10 21 16 50 15 200 55 30 45 45 200 2 50 18 10 21 16 50 15 200 55 30 45 45 200 A A mA mA mA mA A VPP VCC VPP > VCC VPP =VPP1, 2, 3 Program in Progress VPP = VPP4 Program in Progress VPP = VPP1, 2, 3 Program in Progress VPP = VPP4 Program in Progress VPP = VPP1, 2, 3, 4 Program or Erase Suspend in Progress
Note Typ 6
Output Leakage Current VCC Standby Current
6
10
10
10
A
6
18
35
20
50
150
250
A
ICCD
VCC Power-Down Current
6
7
20
7
20
7
20
A
ICCR
VCC Read Current
4,6
10
18
8
15
9
15
mA
IPPD IPPR ICCW+ IPPW
VPP Deep PowerDown Current VPP Read Current VCC + VPP Program Current 3,6
0.2
5
0.2
5
0.2
5
A
ICCE + VCC + VPP Erase IPPE Current
3,6
20 16
IPPES IPPWS
VPP Erase Suspend Current
3
50
PRELIMINARY
25
SMART 3 ADVANCED BOOT BLOCK
4.4
DC Characteristics (Continued)
VCC VCCQ 2.7 V-3.6 V 2.7 V-3.6 V Min -0.4 VCCQ -0.4V 0.10 Max 0.4 2.7 V-2.85 V 1.65 V-2.5 V Min -0.2 VCCQ -0.2V -0.10 0.10 Max 0.2 2.7 V-3.3 V 1.8 V-2.5 V Min -0.2 VCCQ -0.2V -0.10 0.10 Max 0.2
E
Unit Test Conditions V V V VCC = VCCMin VCCQ = VCCQMin IOL = 100 A VCC = VCCMin VCCQ = VCCQMin IOH = -100 A Complete Write Protection VCCQ -0.1V VCCQ -0.1V 1.5 1.5 V V V 2.7 2.85 2.7 3.3 12.6 V V V V V
Sym VIL VIH VOL
Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP Lock-Out Voltage VPP during Program and Erase Operations
Note
VOH
VCCQ -0.1V 2 2 2 2 2,5 11.4 1.5 1.2 12.6 2.7 1.5 3.6
VPPLK VPP1 VPP2 VPP3 VPP4 VLKO VLKO2
11.4 1.5 1.2
12.6
11.4 1.5 1.2
VCC Prog/Erase Lock Voltage VCCQ Prog/Erase Lock Voltage
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25 C. 2. Erase and program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of VPP1, VPP2, VPP3 and VPP4. For read operations or during idle time, a 5 V supply may be applied to VPP indefinitely. However, VPP must be at valid levels for program and erase operations. 3. Sampled, not 100% tested. 4. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation. 5. Applying VPP = 11.4 V-12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.4 for details. For read operations or during idle time, a 5 V supply may be applied to VPP indefinitely. However, VPP must be at valid levels for program and erase operations. 6. Since each column lists specifications for a different VCC and VCCQ voltage range combination, the test conditions VCCMax, VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or VCCQ voltage listed at the top of each column.
26
PRELIMINARY
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VCCQ
SMART 3 ADVANCED BOOT BLOCK
INPUT
0.0
VCCQ 2
TEST POINTS
VCCQ 2
OUTPUT
0580_05
NOTE: AC test inputs are driven at VCCQ for a logic "1" and 0.0V for a logic "0." Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10%-90%) <10 ns. Worst case speed conditions are when VCCQ = VCCQMin.
Figure 5. Input Range and Measurement Points
Test Configuration Component Values for Worst Case Speed Conditions
V CCQ
Test Configuration VCCQ1 Standard Test
R
1
CL (pF) 50 50
R1 () R2 () 25 K 25 K
VCCQ2 Standard Test
Out
16.7 K 16.7 K
Device under Test CL R
2
NOTE: CL includes jig capacitance.
0580_06
NOTE: See table for component values.
Figure 6. Test Configuration
PRELIMINARY
27
SMART 3 ADVANCED BOOT BLOCK
4.5
AC Characteristics --Read Operations(1)
Product 3.0 V-3.6 V 2.7 V-3.6 V 80 ns 90 ns Min 80 80 2 2 80 30 600 3 3 3 3 3 0 0 0 25 25 0 0 0 25 25 0 Max Min 90 90 90 30 600 0 0 25 25 0 Max Min 100 100 100 30 600 0 0 Max 100 ns
E
110 ns Min 110 110 110 30 600 Max Unit ns ns ns ns ns ns ns 25 25 ns ns ns
# R1 R2 R3 R4 R5 R6 R7 R8 R9 R10
Sym tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH
Parameter Read Cycle Time Address to Output Delay CE# to Output Delay OE# to Output Delay RP# to Output Delay CE# to Output in Low Z OE# to Output in Low Z CE# to Output in High Z OE# to Output in High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First
Note
NOTES: 1. See AC Waveform: Read Operations. 2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 3. Sampled, but not 100% tested.
28
PRELIMINARY
E
VIH ADDRESSES (A) VIL CE# (E) VIH VIL VIH OE# (G) VIL VIH WE# (W) VIL VOH DATA (D/Q) VOL RP#(P) VIH VIL High Z
SMART 3 ADVANCED BOOT BLOCK
Device and Address Selection Address Stable R1 Data Valid
Standby
R8
R9 R7 R6 R2 R5
0580_07
R4 R3 Valid Output
R10 High Z
Figure 7. AC Waveform: Read Operations
PRELIMINARY
29
SMART 3 ADVANCED BOOT BLOCK
4.6
AC Characteristics --Write Operations(1)
Product 3.0 V - 3.6 V 2.7 V - 3.6 V # Symbol tPHWL / tPHEL tELWL / tWLEL tELEH / tWLWH tDVWH / tDVEH tAVWH / tAVEH tWHEH / tEHWH tWHDX / tEHDX tWHAX / tEHAX tWHWL / tEHEL tVPWH / tVPEH tQVVL Parameter RP# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold Time from WE# (CE#) High Data Hold Time from WE# (CE#) High Address Hold Time from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) Going High VPP Hold from Valid SRD 2 2 4 3 3 4 2 2 Note Min 600 0 70 50 70 0 0 0 30 200 0 80 90 Min 600 0 70 50 70 0 0 0 30 200 0 Min 600 0 70 60 70 0 0 0 30 200 0 100
E
110 Min 600 0 70 60 70 0 0 0 30 200 0 Unit ns ns ns ns ns ns ns ns ns ns ns
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11
NOTES: 1. Read timing characteristics during program suspend and erase suspend are the same as during read-only operations. 2. Refer to command definition table (Table 6) for valid AIN or DIN. 3. Sampled, but not 100% tested. 4. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
30
PRELIMINARY
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4.7
Symbol tBWPB tBWMB
SMART 3 ADVANCED BOOT BLOCK
Program and Erase Timings
VPP Parameter 8-KB Parameter Block Program Time (Byte) 4-KW Parameter Block Program Time (Word) 64-KB Main Block Program Time (Byte) 32-KW Main Block Program Time(Word) Notes 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2.7 V-3.6 V Typ(1) 0.16 0.10 1.2 0.8 17 22 1 0.5 1 1 5 5 Max 0.48 0.30 3.7 2.4 165 200 4 4 5 5 10 20 11.4 V-12.6 V Typ(1) 0.08 0.03 0.6 0.24 8 8 0.8 0.4 1 0.6 5 5 Max 0.24 0.12 1.7 1 185 185 4 4 5 5 10 20 Units s s s s s s s s s s s s
tWHQV1 / tEHQV1
Byte Program Time Word Program Time
tWHQV2 / tEHQV2
8-KB Parameter Block Erase Time (Byte) 4-KW Parameter Block Erase Time (Word)
tWHQV3 / tEHQV3
64-KB Main Block Erase Time (Byte) 32-KW Main Block Erase Time (Word)
tWHRH1 / tEHRH1 tWHRH2 / tEHRH2
Program Suspend Latency Erase Suspend Latency
NOTES: 1. Typical values measured at nominal voltages and TA = +25 C. 2. Excludes external system-level overhead. 3. Sampled, not 100% tested.
PRELIMINARY
31
SMART 3 ADVANCED BOOT BLOCK
E
C AIN W5 W6 W8 (Note 1) D E F (Note 1) W3 W4 W7 DIN
Valid SRD
VIH
ADDRESSES [A]
A
B AIN
VIL VIH
CE#(WE#) [E(W)]
VIL VIH W2
OE# [G]
VIL VIH
WE#(CE#) [W(E)]
W9
VIL VIH
DATA [D/Q]
High Z
VIL
DIN
DIN
W1
RP# [P]
VIH VIL VIH
WP#
VIL VPPH 2 VPPH1 VPPLK VIL
W10
W11
V
PP
[V]
0580_08
NOTES: 1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status Register Data. A. VCC Power-Up and Standby. B. Write Program or Erase Setup Command. C. Write Valid Address and Data (for Program) or Erase Confirm Command. D. Automated Program or Erase Delay. E. Read Status Register Data (SRD): reflects completed program/erase operation. F. Write Read Array Command.
Figure 8. AC Waveform: Program and Erase Operations
32
PRELIMINARY
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5.0
SMART 3 ADVANCED BOOT BLOCK
RESET OPERATIONS
VIH VIL
RP# (P)
t PLPH (A) Reset during Read Mode
t PHQV t PHWL t PHEL
Abort Complete
t PLRH
RP# (P)
VIH VIL
t PHQV t PHWL t PHEL
t PLPH (B) Reset during Program or Block Erase, t PLPH < t PLRH
Abort Deep Complete PowerDown
RP# (P)
VIH V IL
t PLRH
t PHQV t PHWL t PHEL
t PLPH
(C) Reset Program or Block Erase, t PLPH > t PLRH
0580_09
Figure 9. AC Waveform: Deep Power-Down/Reset Operation Reset Specifications VCC = 2.7 V-3.6 V Symbol tPLPH tPLRH Parameter RP# Low to Reset during Read (If RP# is tied to VCC, this specification is not applicable) RP# Low to Reset during Block Erase or Program Notes 1,3 2,3 Min 100 22 Max Unit ns s
NOTES: 1. If tPLPH is <100 ns the device may still RESET but this is not guaranteed. 2. If RP# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. 3. Sampled, but not 100% tested.
PRELIMINARY
33
SMART 3 ADVANCED BOOT BLOCK
6.0
ORDERING INFORMATION
E
Access Speed (ns) (90, 110) Lithography Not Present = 0.4 m A = 0.25 m T = Top Blocking B = Bottom Blocking Product Family B3 = Smart 3 Advanced Boot Block VCC = 2.7 V - 3.6 V VPP = 2.7 V - 3.6 V or 11.4 V - 12.6 V
T E2 8 F 1 6 0 B3 T A9 0
Package TE = 40-Lead/48-Lead TSOP GT = 48-Ball BGA* CSP Product line designator for all Intel Flash products Device Density 320 = x16 (32 Mbit) 160 = x16 (16 Mbit) 800 = x16 (8 Mbit) 400 = x 16 (4 Mbit) 032 = x 8 (32 Mbit) 016 = x8 (16 Mbit) 008 = x8 (8 Mbit)
34
PRELIMINARY
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Ordering Information Valid Combinations 40-Lead TSOP Ext. Temp. 32 M 48-Ball BGA* CSP(1) GT28F032B3TA95 GT28F032B3BA95 GT28F032B3TA115 GT28F032B3BA115 Ext. Temp. 16 M
TE28F016B3TA90(2) TE28F016B3BA90(2) TE28F016B3TA110(2) TE28F016B3BA110(2) GT28F016B3TA90(2) GT28F016B3BA90(2) GT28F016B3TA110(2) GT28F016B3BA110(2) GT28F008B3T90 GT28F008B3B90 GT28F008B3T110 GT28F008B3B110
SMART 3 ADVANCED BOOT BLOCK
48-Lead TSOP TE28F320B3TA95 TE28F320B3BA95 TE28F320B3TA115 TE28F320B3BA115
TE28F160B3TA90(2) TE28F160B3BA90(2) TE28F160B3TA110(2) TE28F160B3BA110(2) TE28F800B3TA90(2) TE28F800B3BA90(2) TE28F800B3TA110(2) TE28F800B3BA110(2) TE28F400B3T110 TE28F400B3B110
48-Ball BGA CSP GT28F320B3TA95 GT28F320B3BA95 GT28F320B3TA115 GT28F320B3BA115
GT28F160B3TA90(2) GT28F160B3BA90(2) GT28F160B3TA110(2) GT28F160B3BA110(2) GT28F800B3T90 GT28F800B3B90 GT28F800B3T110 GT28F800B3B110
Ext. Temp. 8M
TE28F008B3TA90(2) TE28F008B3BA90(2) TE28F008B3TA110(2) TE28F008B3BA110(2)
Ext. Temp 4M
NOTES: 1. The 48-ball BGA package top side mark reads F160B3 [or F800B3]. This mark is identical for both x8 and x16 products. All product shipping boxes or trays provide the correct information regarding bus architecture. However, once the devices are removed from the shipping media, it may be difficult to differentiate based on the top side mark. The device identifier (accessible through the Device ID command: see Section 3.2.2 for further details) enables x8 and x16 BGA package product differentiation. 2. The second line of the 48-ball BGA package top side mark specifies assembly codes. For samples only, the first character signifies either "E" for engineering samples or "S" for silicon daisy chain samples. All other assembly codes without an "E" or "S" as the first character are production units. 3. Product can be ordered in either 0.25 m or 0.4 m material. The "A" before the access speed specifies 0.25 m material. 4. For new designs, Intel recommends using 0.25 m Advanced Boot Block devices.
PRELIMINARY
35
SMART 3 ADVANCED BOOT BLOCK
7.0
ADDITIONAL INFORMATION (1,2)
Order Number 210830 297948 297835 Document/Tool
E
1997 Flash Memory Databook Smart 3 Advanced Boot Block Flash Memory Family Specification Update 28F160B3 Specification Update Smart 3 Advanced Boot Block Algorithms (`C' and assembly) http://developer.intel.com/design/flcomp
Contact your Intel Representative 297874
Flash Data Integrator (FDI) Software Developer's Kit FDI Interactive: Play with Intel's Flash Data Integrator on Your PC
NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical documentation and tools.
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PRELIMINARY
E
Current State Read Array Read Status Read Identifier Prog. Setup Program (continue) Program Suspend to Read Status Program Suspend to Read Array Prog. Susp. to Read Identifier Program (complete) Erase Setup Erase Cmd. Error Erase (continue) Erase Suspend to Status Erase Susp. to Read Array Erase Susp. to Read Identifier Erase (complete)
SMART 3 ADVANCED BOOT BLOCK
APPENDIX A WRITE STATE MACHINE CURRENT/NEXT STATES
Command Input (and Next State) SR.7 Data When Read Array Status Identifier Status Status Read Array (FFH) Read Array Read Array Read Array Program Setup (10/40H) Program Setup Program Setup Program Setup Erase Setup (20H) Erase Setup Erase Setup Erase Setup Erase Confirm (D0H) Prog/Ers Suspend (B0H) Read Array Read Array Read Array Prog/Ers Resume (D0H) Read Status (70H) Read Status Read Status Read Status Clear Status (50H) Read Array Read Array Read Array Read Identifier. (90H) Read Identifier Read Identifier Read Identifier
"1" "1" "1" "1" "0"
Program (Command Input = Data to be Programmed) Program (continue) Prog. Susp. to Rd. Status Program (continue) Program Susp. to Read Array Program Susp. to Read Array Program Susp. to Read Array Read Array Erase (continue) Erase Cmd. Error Read Array Erase Sus. to Read Status Erase Erase Susp. to Read Array Erase Susp. to Read Array Erase Susp. to Read Array Read Array Erase Erase (continue) Program (continue) Program (continue)
"1"
Status
Prog. Sus. to Read Array Prog. Susp. to Read Array Prog. Susp. to Read Array Read Array
Program Suspend to Read Array
Prog. Susp. to Read Status Prog. Susp. to Read Status Prog. Susp. to Read Status Read Status
Prog. Sus. to Read Array Prog. Sus. to Read Array Prog. Sus. to Read Array Read Array
Prog. Susp. to Read Identifier Prog. Susp. to Read Identifier Prog. Susp. to Read Identifier Read Identifier
"1"
Array
Program Suspend to Read Array
Program (continue)
Program (continue)
"1"
Identifier
Program Suspend to Read Array
Program (continue)
Program (continue)
"1" "1" "1" "0"
Status Status Status Status
Program Setup
Erase Setup
Erase Command Error Read Array Program Setup Erase Setup
Erase Command Error Read Status Read Array Read Identifier
Erase (continue)
Erase (continue)
"1"
Status
Erase Susp. to Read Array Erase Susp. to Read Array Erase Susp. to Read Array Read Array
Program Setup
Erase Susp. to Read Array Erase Susp. to Read Array Erase Susp. to Read Array Erase Setup
Erase Susp. to Read Status Erase Susp. to Read Status Erase Susp. to Read Status Read Status
Erase Susp. to Read Array Erase Susp. to Read Array Erase Susp. to Read Array Read Array
Ers. Susp. to Read Identifier Ers. Susp. to Read Identifier Ers. Susp. to Read Identifier Read Identifier
"1"
Array
Program Setup
Erase
Erase
"1"
Identifier
Program Setup
Erase
Erase
"1"
Status
Program Setup
PRELIMINARY
37
SMART 3 ADVANCED BOOT BLOCK
APPENDIX B ACCESS TIME VS. CAPACITIVE LOAD (tAVQV vs. CL)
E
Access Time vs. Load Capacitance
99 95 Access Time (ns) 91 VCCQ = 2.7V 87 83 79 75 30 40 50 60 70 80 90 100 Load Capacitance (pF) VCCQ = 3.0V
This chart shows a derating curve for device access time with respect to capacitive load. The value in the DC Characteristics section of the specification corresponds to C L = 50 pF.
NOTE: Sampled, but not 100% tested
38
PRELIMINARY
E
VCCQ
SMART 3 ADVANCED BOOT BLOCK
APPENDIX C ARCHITECTURE BLOCK DIAGRAM
DQ0-DQ15
Output Buffer
Input Buffer
Output Multiplexer
Status Register
Data Register
Identifier Register
I/O Logic Command User Interface CE# WE# OE# RP# WP#
Power Reduction Control A0-A19 Y-Decoder Input Buffer 4-KWord Parameter Block
Data Comparator
Y-Gating/Sensing 4-KWord Parameter Block 32-KWord Main Block
Write State Machine 32-KWord Main Block
Program/Erase Voltage Switch
VPP
Address Latch Address Counter
X-Decoder
VCC GND
0580-C1
PRELIMINARY
39
SMART 3 ADVANCED BOOT BLOCK
APPENDIX D WORD-WIDE MEMORY MAP DIAGRAMS
8-Mbit, 16-Mbit, and 32-Mbit Word-Wide Memory Addressing Top Boot Size (KW)
4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
E
32M
1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF
Bottom Boot 32M
1FF000-1FFFFF 1FE000-1FEFFF 1FD000-1FDFFF 1FC000-1FCFFF 1FB000-1FBFFF 1FA000-1FAFFF 1F9000-1F9FFF 1F8000-1F8FFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF
8M
7F000-7FFFF 7E000-7EFFF 7D000-7DFFF 7C000-7CFFF 7B000-7BFFF 7A000-7AFFF 79000-79FFF 78000-78FFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 00000-07FFF
16M
FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 00000-07FFF
Size (KW)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
8M
16M
F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF
0F8000-0FFFFF 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF
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PRELIMINARY
E
Size (KW)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
SMART 3 ADVANCED BOOT BLOCK
8-Mbit, 16-Mbit, and 32-Mbit Word-Wide Memory Addressing (Continued) Top Boot Bottom Boot 32M
0F8000-0FFFFF 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF
8M
16M
Size (KW)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4
8M
16M
C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF
32M
0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
PRELIMINARY
41
SMART 3 ADVANCED BOOT BLOCK
4-Mbit Word-Wide Memory Addressing Top Boot Size (KW)
4 4 4 4 4 4 4 4 32 32 32 32 32 32 32
E
4M
38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-017FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
Bottom Boot 4M
3F000-3FFFF 3E000-3EFFF 3D000-3DFFF 3C000-3CFFF 3B000-3BFFF 3A000-3AFFF 39000-39FFF 38000-38FFF 30000-037FFF 28000-2FFFF 20000-2FFFF 18000-1FFFF 10000-017FFF 08000-0FFFF 00000-07FFF
Size (KW)
32 32 32 32 32 32 32 4 4 4 4 4 4 4 4
42
PRELIMINARY
E
Size (KB)
8 8 8 8 8 8 8 8 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64
SMART 3 ADVANCED BOOT BLOCK
APPENDIX E BYTE-WIDE MEMORY MAP DIAGRAMS
Byte-Wide Memory Addressing Top Boot Bottom Boot 32M
3FE000-3FFFFF 3FC000-3FDFFF 3FA000-3FBFFF 3F8000-3F9FFF 3F6000-3F7FFF 3F4000-3F5FFF 3F2000-3F3FFF 3F0000-3F1FFF 3E0000-3EFFFF 3D0000-3DFFFF 3C0000-3CFFFF 3B0000-3BFFFF 3A0000-3AFFFF 390000-39FFFF 380000-38FFFF 370000-37FFFF 360000-36FFFF 350000-35FFFF 340000-34FFFF 330000-33FFFF 320000-32FFFF 310000-31FFFF 300000-30FFFF 2F0000-2FFFFF 2E0000-2EFFFF 2D0000-2DFFFF 2C0000-2CFFFF 2B0000-2BFFFF 2A0000-2AFFFF 290000-29FFFF 280000-28FFFF 270000-27FFFF 260000-26FFFF 250000-25FFFF 240000-24FFFF 230000-23FFFF 220000-22FFFF 210000-21FFFF 200000-20FFFF
8M
FE000-FFFFF FC000-FDFFF FA000-FBFFF F8000-F9FFF F6000-F7FFF F4000-F5FFF F2000-F3FFF F0000-F1FFF E0000-EFFFF D0000-DFFFF C0000-CFFFF B0000-BFFFF A0000-AFFFF 90000-9FFFF 80000-8FFFF 70000-7FFFF 60000-6FFFF 50000-5FFFF 40000-4FFFF 30000-3FFFF 20000-2FFFF 10000-1FFFF 00000-0FFFF
16M
1FE000-1FFFFF 1FC000-1FDFFF 1FA000-1FBFFF 1F8000-1F9FFF 1F6000-1F7FFF 1F4000-1F5FFF 1F2000-1F3FFF 1F0000-1F1FFF 1E0000-1EFFFF 1D0000-1DFFFF 1C0000-1CFFFF 1B0000-1BFFFF 1A0000-1AFFFF 190000-19FFFF 180000-18FFFF 170000-17FFFF 160000-16FFFF 150000-15FFFF 140000-14FFFF 130000-13FFFF 120000-12FFFF 110000-11FFFF 100000-10FFFF 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 000000-00FFFF
Size (KB)
64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64
8M
16M
32M
3F0000-3FFFFF 3E0000-3EFFFF 3D0000-3DFFFF 3C0000-3CFFFF 3B0000-3BFFFF 3A0000-3AFFFF 390000-39FFFF 380000-38FFFF 370000-37FFFF 360000-36FFFF 350000-35FFFF 340000-34FFFF 330000-33FFFF 320000-32FFFF 310000-31FFFF 300000-30FFFF 2F0000-2FFFFF 2E0000-2EFFFF 2D0000-2DFFFF 2C0000-2CFFFF 2B0000-2BFFFF 2A0000-2AFFFF 290000-29FFFF 280000-28FFFF 270000-27FFFF 260000-26FFFF 250000-25FFFF 240000-24FFFF 230000-23FFFF 220000-22FFFF 210000-21FFFF 200000-20FFFF
1F0000-1FFFFF 1E0000-1EFFFF 1D0000-1DFFFF 1C0000-1CFFFF 1B0000-1BFFFF 1A0000-1AFFFF 190000-19FFFF
1F0000-1FFFFF 1E0000-1EFFFF 1D0000-1DFFFF 1C0000-1CFFFF 1B0000-1BFFFF 1A0000-1AFFFF 190000-19FFFF
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PRELIMINARY
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SMART 3 ADVANCED BOOT BLOCK
Byte-Wide Memory Addressing (Continued) Top Boot Size (KB)
64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64
E
16M
180000-18FFFF 170000-17FFFF 160000-16FFFF 150000-15FFFF 140000-14FFFF 130000-13FFFF 120000-12FFFF 110000-11FFFF 100000-10FFFF
Bottom Boot 32M
1F0000-1FFFFF 1E0000-1EFFFF 1D0000-1DFFFF 1C0000-1CFFFF 1B0000-1BFFFF 1A0000-1AFFFF 190000-19FFFF 180000-18FFFF 170000-17FFFF 160000-16FFFF 150000-15FFFF 140000-14FFFF 130000-13FFFF 120000-12FFFF 110000-11FFFF 100000-10FFFF 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 000000-00FFFF
8M
16M
Size (KB)
64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 8 8 8 8 8 8 8 8
8M
32M
180000-18FFFF 170000-17FFFF 160000-16FFFF 150000-15FFFF 140000-14FFFF 130000-13FFFF 120000-12FFFF 110000-11FFFF 100000-10FFFF 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 00E000-00FFFF 00C000-00DFFF 00A000-00BFFF 008000-009FFF 006000-007FFF 004000-005FFF 002000-003FFF 000000-001FFF
F0000-FFFFF E0000-EFFFF D0000-DFFFF C0000-CFFFF B0000-BFFFF A0000-AFFFF 90000-9FFFF 80000-8FFFF 70000-7FFFF 60000-6FFFF 50000-5FFFF 40000-4FFFF 30000-3FFFF 20000-2FFFF 10000-1FFFF 0E000-0FFFF 0C000-0DFFF 0A000-0BFFF 08000-09FFF 06000-07FFF 04000-05FFF 02000-03FFF 00000-01FFF
0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 00E000-00FFFF 00C000-00DFFF 00A000-00BFFF 008000-009FFF 006000-007FFF 004000-005FFF 002000-003FFF 000000-001FFF
44
PRELIMINARY
E
Start
SMART 3 ADVANCED BOOT BLOCK
APPENDIX F PROGRAM AND ERASE FLOWCHARTS
Bus Operation Write Write
Command Program Setup Program
Comments Data = 40H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 40H
Program Address/Data
Read
Read Status Register
Standby
SR.7 = 1? Yes Full Status Check if Desired
No
Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode.
Program Complete
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.4 = 0 1 SR.1 = 0 Program Successful
If an error is detected, clear the status register before attempting retry or other error recovery.
0580_E1
Bus Operation Standby
Command
Comments Check SR.3 1 = VPP Low Detect Check SR.4 1 = VPP Program Error Check SR.1 1 = Attempted Program to Locked Block - Program Aborted
VPP Range Error 1 Programming Error
Standby
Standby
SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine.
Attempted Program to Locked Block - Aborted
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are programmed before full status is checked.
Figure 10. Program Flowchart
PRELIMINARY
45
SMART 3 ADVANCED BOOT BLOCK
E
Bus Operation Write Command Program Suspend Read Status Comments Data = B0H Addr = X Data=70H Addr=X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.2 1 = Program Suspended 0 = Program Completed Data = FFH Addr = X Read array data from block other than the one being programmed. Data = D0H Addr = X Write Read Read Standby Standby Standby Standby Write Write Read Read Array Read Array
Start
Write B0H
Write 70H
Read Status Register
SR.7 = 1 SR.2 = 1
0
0
Program Completed
Read Write Write
Program Resume Program Resume
Write FFH
Read Array Data
Done Reading Yes Write D0H
No
Write FFH
Program Resumed
Read Array Data
0580_E2
Figure 11. Program Suspend/Resume Flowchart
46
PRELIMINARY
E
Start Write 20H
Write
SMART 3 ADVANCED BOOT BLOCK
Bus Operation
Command
Comments Data = 20H Addr = Within Block to Be Erased Data = D0H Addr = Within Block to Be Erased Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Erase Setup
Write D0H and Block Address
Write
Erase Confirm
Read
Read Status Register No
Suspend Erase Loop 0 Suspend Erase Yes
Standby
SR.7 = 1 Full Status Check if Desired
Repeat for subsequent block erasures. Full Status Check can be done after each block erase or after a sequence of block erasures. Write FFH after the last write operation to reset device to read array mode.
Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.4,5 = 0 1 SR.5 = 0 1 SR.1 = 0 Block Erase Successful
0580_E3
Bus Operation Standby
Command
Comments Check SR.3 1 = VPP Low Detect Check SR.4,5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error Check SR.1 1 = Attempted Erase of Locked Block - Erase Aborted
VPP Range Error
Standby
1
Command Sequence Error
Standby
Standby
Block Erase Error
SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine. SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Attempted Erase of Locked Block - Aborted
Figure 12. Block Erase Flowchart
PRELIMINARY
47
SMART 3 ADVANCED BOOT BLOCK
E
Bus Operation Write Command Comments Program Data = B0H Erase Suspend Suspend Addr = X Read Status Data=70H Addr=X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Erase Suspended 0 = Erase Completed Data = FFH Addr = X Read array data from block other than the one being erased. Data = D0H Addr = X Write Read Read Standby Standby Standby Standby Write Write Read Read Array Read Array
Start
Write B0H
Write 70H
Read Status Register
SR.7 = 1 SR.6 = 1
0
0
Erase Completed
Read Write Write
Program Resume Erase Resume
Write FFH
Read Array Data
Done Reading Yes Write D0H
No
Write FFH
Erase Resumed
Read Array Data
0580_E4
Figure 13. Erase Suspend/Resume Flowchart
48
PRELIMINARY

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